As semiconductor device dimensions get smaller, and device density increases, it becomes more and more difficult to build an efficient and reliable isolation process to separate active devices. One drawback with the LOCal Oxidation of Silicon (LOCOS) is the decreasing pad thickness which makes etch steps more difficult.
The process of the present invention provides a new nitride etch that is suitable for etching submicron features, and that stops on a thin pad oxide without substantially pitting the underlying silicon. These characteristics make the process of the present invention well suited for use in the conventional LOCOS process.
The process of the present invention, provides no significant center to edge "loading" effect. Center to edge "loading" effect refers to a characteristic non-uniformity in etching wherein the center of a wafer etches at a slower rate than the edges, thereby resulting in a wafer which is thicker in the center than at the edges. If there is very little center to edge "loading" effect, then the etch uniformity across the wafer will be very good.
Previous technologies consist of the following etch chemistries: SF.sub.6 /HeO.sub.2, CF.sub.4 /CHF.sub.3, NF.sub.3 /HBr, NF.sub.3 HCl, NF.sub.3 /Cl.sub.2, NF.sub.3 /O.sub.2. These processes tend to have problems associated with them. The processes containing Cl.sub.2 in the overetch tend to exhibit trenching in the tight areas.
The processes containing carbon, sulfur, or bromine tend to be dirty. Dirty processes cause wafer and chamber contamination. Dirty processes also cause build up of contamination in the tight areas of the wafer, thereby causing "micro-loading."
"Micro-loading" refers to uneven etching of the wafer. If there is less "micro-loading", then the "open" and "tight" areas will etch at substantially the same rate. "Open" refers to the less confined spaces of the semiconductor device, such as the periphery of the device or the scribe lines, which tend to etch at a faster rate than "tight" areas. "Tight" refers to the more constricted areas of the semiconductor device, such as the area within the array and the runners between transistors.
These and other known processes suffer from either poor "loading" effects, poor uniformity, or poor nitride to oxide selectivity, which will make these processes inadequate for etching submicron nitride features.
The process using NF.sub.3 /O.sub.2 also has drawbacks. One of the problems relates to the effectiveness of NF.sub.3 /O.sub.2 as an etchant of photoresist. Hence, the process will suffer from excessive photoresist loss, and a large disparity between the critical dimensions measured: 1) during an inspection after development, i.e., after the photolithography patterning step, and 2) during an inspection after clean, i.e., after the wafer has been etched. The disparity in the dimensions results due to resist erosion.
The process of the present invention is clean, in addition to having high nitride to oxide selectivity, good resist selectivity, good uniformity, and substantially no "micro-loading."